On Mon, Mar 28, 2016 at 03:40:58PM -0500, Matthew McClintock wrote: > On Mar 28, 2016, at 1:13 PM, Guenter Roeck <linux@xxxxxxxxxxxx> wrote: > > > >>> bit 0 is the enable bit, and bit 1 enables interrupts. At address 0x08 (eg > >>> LPASS_QDSP6SS_WDOG_UNMASKED_INT_EN), bit 0 enables interrupts and bit 1 is > >>> undefined. > >> > >> I honestly don’t see anything at 0x8 for either blocks that looks like this. For the new block bit 0 is enabling and bit 1 enabled interrupts. > >> > > That is from the APQ8064 datasheet. > > So taken from the timer offset 0x0208A000 I just have a generic counter register CPU0_APCS_GPT0_CNT at 0x8 > > What doc are you looking at? > "Qualcomm Snapdragon 600 Processor APQ8064 Hardware Register Description" It is available for download from the Qualcomm web site. See chapter 12.10.3, "Watchdog timer registers". The register block is at 0x28882000. Registers are almost the same, except for the offset and the definition of the bits in the enable register. LPASS is "Low Power Audio Subsystem". Maybe it has its own watchdog. Guenter -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
