On 6/6/24 15:26, Konrad Dybcio wrote:
On 4.06.2024 3:11 AM, Sibi Sankar wrote:
Add the CPU and LLCC BWMONs on X1E80100 SoCs.
Hey Konrad,
Thanks for taking time to review the series :)
Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++
1 file changed, 169 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 1929c34ae70a..d86c4d3be126 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 {
};
};
+ pmu@24091000 {
+ compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0 0x24091000 0 0x1000>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>;
QCOM_ICC_TAG_ACTIVE_ONLY
ack
[...]
+
+ cpu0_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
I *think* if you add opp-shared here, you can reference the same OPP table
from all 3 BWMONs without anything exploding.
I did try this out before IIRC this resulted in just one device vote
in the interconnect_summary. Didn't investigate further before because
it was breaking bindings anyway. Will have another look at it.
-Sibi
Konrad
