On 6/6/24 14:39, Shivnandan Kumar wrote:
On 6/4/2024 6:41 AM, Sibi Sankar wrote:
Add the CPU and LLCC BWMONs on X1E80100 SoCs.
Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
Hey Shiv,
Thanks for taking time to review the series :)
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 169 +++++++++++++++++++++++++
1 file changed, 169 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 1929c34ae70a..d86c4d3be126 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5329,6 +5329,175 @@ cpu_scp_lpri1: scp-sram-section@200 {
};
};
+ pmu@24091000 {
+ compatible = "qcom,x1e80100-llcc-bwmon",
"qcom,sc7280-llcc-bwmon";
+ reg = <0 0x24091000 0 0x1000>;
+
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+
+ interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt
SLAVE_EBI1 3>;
+
+ operating-points-v2 = <&llcc_bwmon_opp_table>;
+
+ llcc_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
Nitpick,In one table, we start from ‘opp-0,’ while in the other table,
it begins with ‘opp-1,it is better to make it consistent across table.
Will fix it in the next re-spin.
-Sibi
+ opp-peak-kBps = <800000>;
reg = <0 0x25000000 0 0x200000>,
...
[snip]
...
Thanks,
Shivnandan
