Hello Abhinav Kumar,
Commit d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_*
for writeback") from Apr 26, 2022 (linux-next), leads to the
following Smatch static checker warning:
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c:546 dpu_encoder_phys_wb_disable()
error: we previously assumed 'phys_enc->hw_ctl->ops.clear_pending_flush' could be null (see line 532)
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
519 static void dpu_encoder_phys_wb_disable(struct dpu_encoder_phys *phys_enc)
520 {
521 struct dpu_hw_wb *hw_wb = phys_enc->hw_wb;
522 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl;
523
524 DPU_DEBUG("[wb:%d]\n", hw_wb->idx - WB_0);
525
526 if (phys_enc->enable_state == DPU_ENC_DISABLED) {
527 DPU_ERROR("encoder is already disabled\n");
528 return;
529 }
530
531 /* reset h/w before final flush */
532 if (phys_enc->hw_ctl->ops.clear_pending_flush)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Probably this check can be deleted
533 phys_enc->hw_ctl->ops.clear_pending_flush(phys_enc->hw_ctl);
534
535 /*
536 * New CTL reset sequence from 5.0 MDP onwards.
537 * If has_3d_merge_reset is not set, legacy reset
538 * sequence is executed.
539 *
540 * Legacy reset sequence has not been implemented yet.
541 * Any target earlier than SM8150 will need it and when
542 * WB support is added to those targets will need to add
543 * the legacy teardown sequence as well.
544 */
545 if (hw_ctl->caps->features & BIT(DPU_CTL_ACTIVE_CFG))
--> 546 dpu_encoder_helper_phys_cleanup(phys_enc);
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Because dpu_encoder_helper_phys_cleanup() calls it without checking at
on the last line in the function.
547
548 phys_enc->enable_state = DPU_ENC_DISABLED;
549 }
regards,
dan carpenter
