On Fri, May 31, 2024 at 08:00:32PM +0300, Abel Vesa wrote:
> So the PCIe 6 can be configured in 4-lane mode or 2-lane mode. For
s/So the PCIe 6/The PCIe 6a controller and PHY/
> 4-lane mode, it fetches the lanes provided by PCIe 6b. For 2-lane mode,
s/fetches/uses/
> PCIe 6a uses 2 lanes and then PCIe 6b uses the other 2 lanes. Configure
> it in 4-lane mode and then each board can configure it depending on the
> design. Both the QCP and CRD boards, currently upstream, use the 6a for
s/use the/use PCIe 6a/
> NVMe in 4-lane mode. Also, mark the controller as 4-lane as well.
>
> Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes")
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> @@ -2903,19 +2903,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> };
>
> pcie6a_phy: phy@1bfc000 {
> - compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";
> - reg = <0 0x01bfc000 0 0x2000>;
> + compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
> + reg = <0 0x01bfc000 0 0x2000>,
> + <0 0x01bfe000 0 0x2000>;
>
> clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
> <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
> <&rpmhcc RPMH_CXO_CLK>,
> <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
> - <&gcc GCC_PCIE_6A_PIPE_CLK>;
This one should not be removed as was already pointed out.
> + <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;
> clock-names = "aux",
> "cfg_ahb",
> "ref",
> "rchng",
> - "pipe";
> + "pipe",
> + "pipediv2";
>
> resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
> <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
> @@ -2927,6 +2929,8 @@ pcie6a_phy: phy@1bfc000 {
>
> power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
>
> + qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
> +
> #clock-cells = <0>;
> clock-output-names = "pcie6a_pipe_clk";
As I just mentioned in my reply on the PHY patch, this does not seem to
work on the CRD were the link still come up as 2-lane (also with the
clocks fixed):
qcom-pcie 1bf8000.pci: PCIe Gen.4 x2 link up
So something appears to be wrong here or in the PHY changes.
Johan
