On 4/25/2024 7:47 AM, Dmitry Baryshkov wrote:
On Wed, 24 Apr 2024 at 05:46, Tengfei Fan <quic_tengfan@xxxxxxxxxxx> wrote:
AIM300 Series is a highly optimized family of modules designed to
support AIoT applications. It integrates QCS8550 SoC, UFS and PMIC
chip etc.
Here is a diagram of AIM300 SoM:
+----------------------------------------+
|AIM300 SoM |
| |
| +-----+ |
| |--->| UFS | |
| | +-----+ |
| | |
| | |
3.7v | +-----------------+ | +---------+ |
---------->| PMIC |----->| QCS8550 | |
| +-----------------+ +---------+ |
| | |
| | |
| | +-----+ |
| |--->| ... | |
| +-----+ |
| |
+----------------------------------------+
Co-developed-by: Fenglin Wu <quic_fenglinw@xxxxxxxxxxx>
Signed-off-by: Fenglin Wu <quic_fenglinw@xxxxxxxxxxx>
Signed-off-by: Tengfei Fan <quic_tengfan@xxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi | 403 +++++++++++++++++++
1 file changed, 403 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/qcs8550-aim300.dtsi
+
+&pcie_1_phy_aux_clk {
+ clock-frequency = <1000>;
+};
Please rebase on top of
https://lore.kernel.org/linux-arm-msm/20240422-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v4-0-868b15a17a45@xxxxxxxxxx/
Sure, I will reabse on the top of this patch series in the new version
patch series
+
+&pcie1 {
+ perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
Please add pinctrl configurations for pcie0 and pcie1
With that fixed:
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
The pinctrl configurations of pcie0 and pcie1 will be moved to this dtsi
file from Carrier Board dts file.
+};
+
--
With best wishes
Dmitry
--
Thx and BRs,
Tengfei Fan
