> > Currently the DWC3 driver supports only single port controller which requires at > most two PHYs ie HS and SS PHYs. There are SoCs that has > DWC3 controller with multiple ports that can operate in host mode. > Some of the port supports both SS+HS and other port supports only HS mode. > > This change primarily refactors the Phy logic in core driver to allow multiport > support with Generic Phy's. > > The DWC3 controller supports up to 15 High-Speed phys and 4 SuperSpeed phys. > The multiport controller in Qualcomm SA8295P is paired with two High-Speed + > SuperSpeed and two High-Speed-only ports. It is assumed that the N > SuperSpeed PHYs are paired with the first N High-Speed PHYs. > Hi All, Thinh Can DW multiple port host patches be (patch 1-4) accepted first? Other multiport vendor will use this.
