On Wed, Apr 17, 2024 at 06:58:54PM +0530, Sibi Sankar wrote:
> Resize the GICR register region as it currently seeps into the CPU Control
> Processor mailbox RX region.
>
Not that anyone is running a stable kernel here, but please make a habit
of adding Fixes: tags when correcting previous mistakes.
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> ---
>
> v2:
> * Pickup Rb from Dimitry.
>
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index f5a3b39ae70e..28f65296781d 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -4949,7 +4949,7 @@ apps_smmu: iommu@15000000 {
> intc: interrupt-controller@17000000 {
> compatible = "arm,gic-v3";
> reg = <0 0x17000000 0 0x10000>, /* GICD */
> - <0 0x17080000 0 0x480000>; /* GICR * 12 */
> + <0 0x17080000 0 0x380000>; /* GICR * 12 */
>
The 12th GICR ends a bit before that, and per your commit message you're
just nudging it down to get this range out of the say of your other
range - rather than giving it a proper value.
Wouldn't 0x300000 be a better value here? Or am I perhaps missing
something in the difference? If so, I'd like the commit message to state
what, so someone doesn't get excited and correct/break it later.
Regards,
Bjorn
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>
> --
> 2.34.1
>
