On Mon, Apr 15, 2024 at 04:49:05PM +0800, Qiang Yu wrote:
bus: mhi: host: pci_generic: Add support for triggering EDL mode in modems
> Add mhi_pci_generic_edl_trigger as edl_trigger for some devices (eg. SDX65)
> to enter EDL mode by writing the 0xEDEDEDED cookie to the channel 91
> doorbell register and forcing an SOC reset afterwards.
>
'Some of the MHI modems like SDX65 based ones are capable of entering the EDL
mode as per the standard triggering mechanism defined in the MHI spec <enter
spec version>. So let's add a common mhi_pci_generic_edl_trigger() function that
triggers the EDL mode in the device when user writes to the <insert full sysfs
entry here> file.'
> Signed-off-by: Qiang Yu <quic_qianyu@xxxxxxxxxxx>
> ---
> drivers/bus/mhi/host/pci_generic.c | 47 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_generic.c
> index 51639bf..cbf8a58 100644
> --- a/drivers/bus/mhi/host/pci_generic.c
> +++ b/drivers/bus/mhi/host/pci_generic.c
> @@ -27,12 +27,19 @@
> #define PCI_VENDOR_ID_THALES 0x1269
> #define PCI_VENDOR_ID_QUECTEL 0x1eac
>
> +#define MHI_EDL_DB 91
> +#define MHI_EDL_COOKIE 0xEDEDEDED
> +
> +/* Device can enter EDL by first setting edl cookie then issuing inband reset*/
> +#define MHI_PCI_GENERIC_EDL_TRIGGER BIT(0)
This is not needed as of now. Let the edl_trigger be bool for now. When vendors
want to add their own methods of triggering EDL, we can extend it.
> +
> /**
> * struct mhi_pci_dev_info - MHI PCI device specific information
> * @config: MHI controller configuration
> * @name: name of the PCI module
> * @fw: firmware path (if any)
> * @edl: emergency download mode firmware path (if any)
> + * @edl_trigger: each bit represents a different way to enter EDL
'capable of triggering EDL mode in the device (if supported)'
> * @bar_num: PCI base address register to use for MHI MMIO register space
> * @dma_data_width: DMA transfer word size (32 or 64 bits)
> * @mru_default: default MRU size for MBIM network packets
> @@ -44,6 +51,7 @@ struct mhi_pci_dev_info {
> const char *name;
> const char *fw;
> const char *edl;
> + unsigned int edl_trigger;
> unsigned int bar_num;
> unsigned int dma_data_width;
> unsigned int mru_default;
> @@ -292,6 +300,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx75_info = {
> .name = "qcom-sdx75m",
> .fw = "qcom/sdx75m/xbl.elf",
> .edl = "qcom/sdx75m/edl.mbn",
> + .edl_trigger = MHI_PCI_GENERIC_EDL_TRIGGER,
> .config = &modem_qcom_v2_mhiv_config,
> .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> .dma_data_width = 32,
> @@ -302,6 +311,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {
> .name = "qcom-sdx65m",
> .fw = "qcom/sdx65m/xbl.elf",
> .edl = "qcom/sdx65m/edl.mbn",
> + .edl_trigger = MHI_PCI_GENERIC_EDL_TRIGGER,
> .config = &modem_qcom_v1_mhiv_config,
> .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> .dma_data_width = 32,
> @@ -312,6 +322,7 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {
> .name = "qcom-sdx55m",
> .fw = "qcom/sdx55m/sbl1.mbn",
> .edl = "qcom/sdx55m/edl.mbn",
> + .edl_trigger = MHI_PCI_GENERIC_EDL_TRIGGER,
> .config = &modem_qcom_v1_mhiv_config,
> .bar_num = MHI_PCI_DEFAULT_BAR_NUM,
> .dma_data_width = 32,
> @@ -928,6 +939,39 @@ static void health_check(struct timer_list *t)
> mod_timer(&mhi_pdev->health_check_timer, jiffies + HEALTH_CHECK_PERIOD);
> }
>
> +static int mhi_pci_generic_edl_trigger(struct mhi_controller *mhi_cntrl)
> +{
> + void __iomem *base = mhi_cntrl->regs;
> + void __iomem *edl_db;
> + int ret;
> + u32 val;
> +
> + ret = mhi_device_get_sync(mhi_cntrl->mhi_dev);
> + if (ret) {
> + dev_err(mhi_cntrl->cntrl_dev, "Wake up device fail before trigger EDL\n");
'Failed to wakeup the device'
- Mani
--
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