On 10/04/2024 09:49, Vladimir Zapolskiy wrote: > Qualcomm SM8650 SoC has three CCI controllers with two I2C busses > connected to each of them. > > The CCI controllers on SM8650 are compatible with the ones found on > many other older generations of Qualcomm SoCs. > > Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@xxxxxxxxxx> > --- > The change is based and depends on a patch series from Jagadeesh Kona: > > https://lore.kernel.org/linux-arm-msm/20240321092529.13362-1-quic_jkona@xxxxxxxxxxx/ > > It might be an option to add this change right to the series, > since it anyway requires a respin. > > A new compatible value "qcom,sm8650-cci" is NOT added to > Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml , because > the controller IP description and selection is covered by a generic > compatible value "qcom,msm8996-cci". I do not understand this reasoning. So you introduce known errors because errors are ok? How does it pass dtbs_check validation? Best regards, Krzysztof
