On several Qualcomm platforms DisplayPort link clocks used incorrect
frequency tables. Drop frequency tables and use clk_byte2_ops instead of
clk_rcg2_ops.
Note, this was tested on SM8450 only and then extended to other
platforms.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
---
Dmitry Baryshkov (4):
clk: qcom: dispcc-sm8450: fix DisplayPort clocks
clk: qcom: dispcc-sm6350: fix DisplayPort clocks
clk: qcom: dispcc-sm8550: fix DisplayPort clocks
clk: qcom: dispcc-sm8650: fix DisplayPort clocks
drivers/clk/qcom/dispcc-sm6350.c | 11 +----------
drivers/clk/qcom/dispcc-sm8450.c | 20 ++++----------------
drivers/clk/qcom/dispcc-sm8550.c | 20 ++++----------------
drivers/clk/qcom/dispcc-sm8650.c | 20 ++++----------------
4 files changed, 13 insertions(+), 58 deletions(-)
---
base-commit: 8568bb2ccc278f344e6ac44af6ed010a90aa88dc
change-id: 20240408-dispcc-dp-clocks-5ee5d5926346
Best regards,
--
Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
