On 4/4/2024 4:43 PM, Stephen Boyd wrote:
Commit ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to
setup clocks") changed the offset that is used to write to
DP_PHY_VCO_DIV from QSERDES_V3_DP_PHY_VCO_DIV to
QSERDES_V4_DP_PHY_VCO_DIV. Unfortunately, this offset is different
between v3 and v4 phys:
#define QSERDES_V3_DP_PHY_VCO_DIV 0x064
#define QSERDES_V4_DP_PHY_VCO_DIV 0x070
meaning that we write the wrong register on v3 phys now. Add another
generic register to 'regs' and use it here instead of a version specific
define to fix this.
This was discovered after Abhinav looked over register dumps with me
from sc7180 Trogdor devices that started failing to light up the
external display with v6.6 based kernels. It turns out that some
monitors are very specific about their link clk frequency and if the
default power on reset value is still there the monitor will show a
blank screen or a garbled display. Other monitors are perfectly happy to
get a bad clock signal.
Cc: Douglas Anderson <dianders@xxxxxxxxxxxx>
Cc: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
Cc: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Fixes: ec17373aebd0 ("phy: qcom: qmp-combo: extract common function to setup clocks")
Signed-off-by: Stephen Boyd <swboyd@xxxxxxxxxxxx>
---
drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
I cross-checked the foll chipsets which use qmp_v3_usb3phy_regs_layout:
-> sdm845
-> sc7180
-> sm6350
All of them have VCO_DIV at offset 0x64.
And, I cross-checked the foll chipsets which use
qmp_v45_usb3phy_regs_layout:
-> sc8180x
-> x1e80100
-> sm8250
-> sm8350
All of them have VCO_DIV at offset 0x70.
Now, thing look in order to me.
Hence,
Reviewed-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
