On some of Qualcomm platform, firmware configures PCIe controller in RC mode with static iATU window mappings of configuration space for entire supported bus range in ECAM compatible mode. Firmware also manages PCIe PHY as well required system resources. Here document properties and required configuration to power up QCOM PCIe ECAM compatible root complex and PHY for PCIe functionality. Signed-off-by: Mayank Rana <quic_mrana@xxxxxxxxxxx> --- .../devicetree/bindings/pci/qcom,pcie-ecam.yaml | 94 ++++++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml new file mode 100644 index 00000000..c209f12 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ecam.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/qcom,pcie-ecam.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm ECAM compliant PCI express root complex + +description: | + Qualcomm SOC based ECAM compatible PCIe root complex supporting MSI controller. + Firmware configures PCIe controller in RC mode with static iATU window mappings + of configuration space for entire supported bus range in ECAM compatible mode. + +maintainers: + - Mayank Rana <quic_mrana@xxxxxxxxxxx> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/power-domain/power-domain-consumer.yaml + +properties: + compatible: + const: qcom,pcie-ecam-rc + + reg: + minItems: 1 + description: ECAM address space starting from root port till supported bus range + + interrupts: + minItems: 1 + maxItems: 8 + + ranges: + minItems: 2 + maxItems: 3 + + iommu-map: + minItems: 1 + maxItems: 16 + + power-domains: + maxItems: 1 + description: A phandle to node which is able support way to communicate with firmware + for enabling PCIe controller and PHY as well managing all system resources needed to + make both controller and PHY operational for PCIe functionality. + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - ranges + - power-domains + - device_type + - linux,pci-domain + - bus-range + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + pcie0: pci@1c00000 { + compatible = "qcom,pcie-ecam-rc"; + reg = <0x4 0x00000000 0 0x10000000>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0x0 0x40000000 0x0 0x40000000 0x0 0x100000>, + <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>, + <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x100000>; + bus-range = <0x00 0xff>; + dma-coherent; + linux,pci-domain = <0>; + power-domains = <&scmi5_pd 0>; + power-domain-names = "power"; + iommu-map = <0x0 &pcie_smmu 0x0000 0x1>, + <0x100 &pcie_smmu 0x0001 0x1>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... -- 2.7.4
