On Fri, Mar 15, 2024 at 11:16:59AM +0100, Konrad Dybcio wrote: > On 2/16/24 07:52, Johan Hovold wrote: > > This makes no sense. As Bjorn already said, you're just polling for the > > link to come up (for a second). And unless you have something else that > > depends on the write to have reached the device, there is no need to > > read it back. It's not going to be cached indefinitely if that's what > > you fear. > > The point is, if we know that the hardware is expected to return "done" > within the polling timeout value of receiving the request to do so, we > are actively taking away an unknown amount of time from that timeout. We're talking about microseconds, not milliseconds or seconds as you seem to believe. > So, if the polling condition becomes true after 980ms, but due to write > buffering the value reached the PCIe hardware after 21 ms, we're gonna > hit a timeout. Or under truly extreme circumstances, the polling may > time out before the write has even arrived at the PCIe hw. So the write latency is not an issue here. Johan
