On Wed, Mar 06, 2024 at 03:51:58PM +0530, Manivannan Sadhasivam wrote:
> In the case of Hyper DMA (HDMA) present in DWC controllers, there is no way
> the drivers can auto detect the number of read/write channels as like its
> predecessor embedded DMA (eDMA). So the glue drivers making use of HDMA
> have to pass the channels count during probe.
>
> To accommodate that, let's skip the existing auto detection of channels
> count procedure for HDMA based platforms. If the channels count passed by
> the glue drivers were wrong in any form, then the existing sanity check
> will catch it.
>
> Suggested-by: Serge Semin <fancer.lancer@xxxxxxxxx>
> Reviewed-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
> Reviewed-by: Frank Li <Frank.Li@xxxxxxx>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
Reviewed-by: Serge Semin <fancer.lancer@xxxxxxxxx>
Please find a tiny nitpick further below.
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 15 ++++++++++-----
> 1 file changed, 10 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 3a26dfc5368f..599991b7ffb2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -927,13 +927,18 @@ static int dw_pcie_edma_find_channels(struct dw_pcie *pci)
> {
> u32 val;
>
> - if (pci->edma.mf == EDMA_MF_EDMA_LEGACY)
> - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL);
> - else
> + /*
> + * Autodetect the read/write channels count only for non-HDMA platforms.
> + * HDMA platforms doesn't support autodetect, so the glue drivers should've
> + * passed the valid count already. If not, the below sanity check will
> + * catch it.
> + */
This is correct for the _native_ HDMA CSRs mapping. I suggest to emphasize
that in the note above.
-Serge(y)
> + if (pci->edma.mf != EDMA_MF_HDMA_NATIVE) {
> val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL);
>
> - pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val);
> - pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val);
> + pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val);
> + pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val);
> + }
>
> /* Sanity check the channels count if the mapping was incorrect */
> if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH ||
>
> --
> 2.25.1
>
