On 08/03/2024 12:40, Satya Priya Kakitapalli (Temp) wrote:
If BIT(0) is set from probe, during any active usecase, the clock gets turned ON automatically when the power domain is turned ON.
Sounds like a very dirty hack really doesn't it. Can you point out where ?
But when we use CLK_IS_CRITICAL flag, the framework keeps the power domain ON and doesn't let the power domain to turn off even when there is no active usecase.
--- bod
