On Wed, 6 Mar 2024 at 14:31, Chukun Pan <amadeus@xxxxxxxxxx> wrote:
>
> Add node to support mmc controller inside of IPQ6018.
> This controller supports both eMMC and SD cards.
>
> Tested with:
> eMMC (HS200)
> SD Card (SDR50/SDR104)
>
> Signed-off-by: Chukun Pan <amadeus@xxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/ipq6018.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> index 322eced0b876..420c192bccd9 100644
> --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
> @@ -441,6 +441,25 @@ dwc_1: usb@7000000 {
> };
> };
>
> + sdhc: mmc@7804000 {
> + compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x07804000 0x0 0x1000>,
> + <0x0 0x07805000 0x0 0x1000>;
> + reg-names = "hc", "cqhci";
> +
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC1_AHB_CLK>,
> + <&gcc GCC_SDCC1_APPS_CLK>,
> + <&xo>;
> + clock-names = "iface", "core", "xo";
> + resets = <&gcc GCC_SDCC1_BCR>;
> + max-frequency = <192000000>;
If I understand correctly, GCC_SDCC1_APPS_CLK support frequencies up
to 384 MHz, but here you are limiting it to 192 MHz. Why is it so?
> + status = "disabled";
> + };
> +
> blsp_dma: dma-controller@7884000 {
> compatible = "qcom,bam-v1.7.0";
> reg = <0x0 0x07884000 0x0 0x2b000>;
> --
> 2.25.1
>
>
--
With best wishes
Dmitry
