On Tue, Aug 08, 2023 at 05:58:26PM +0530, Souradeep Chowdhury wrote:
> diff --git a/Documentation/ABI/testing/debugfs-driver-dcc b/Documentation/ABI/testing/debugfs-driver-dcc
> index 27ed5919d21b..7f588580a906 100644
> --- a/Documentation/ABI/testing/debugfs-driver-dcc
> +++ b/Documentation/ABI/testing/debugfs-driver-dcc
> @@ -1,4 +1,4 @@
> -What: /sys/kernel/debug/dcc/.../ready
> +What: /sys/kernel/debug/qcom-dcc/.../ready
> Date: December 2022
Looks like this patch set is getting closer to being accepted, please
keep the date updated accordingly.
> +#define DCC_LL_NUM_INFO 0x10
> +#define DCC_LL_LOCK 0x00
> +#define DCC_LL_CFG 0x04
> +#define DCC_LL_BASE 0x08
> +#define DCC_FD_BASE 0x0c
> +#define DCC_LL_OFFSET 0x80
> +#define DCC_LL_TIMEOUT 0x10
> +#define DCC_LL_INT_ENABLE 0x18
> +#define DCC_LL_INT_STATUS 0x1c
> +#define DCC_LL_SW_TRIGGER 0x2c
> +#define DCC_LL_BUS_ACCESS_STATUS 0x30
> +
> +/* Default value used if a bit 6 in the HW_INFO register is set. */
> +#define DCC_FIX_LOOP_OFFSET 16
> +
> +/* Mask to find version info from HW_Info register */
> +#define DCC_VER_INFO_MASK BIT(9)
> +
> +#define MAX_DCC_OFFSET GENMASK(9, 2)
> +#define MAX_DCC_LEN GENMASK(6, 0)
> +#define MAX_LOOP_CNT GENMASK(7, 0)
> +#define MAX_LOOP_ADDR 10
> +
> +#define DCC_ADDR_DESCRIPTOR 0x00
> +#define DCC_ADDR_LIMIT 27
> +#define DCC_WORD_SIZE sizeof(u32)
> +#define DCC_ADDR_RANGE_MASK GENMASK(31, 4)
> +#define DCC_LOOP_DESCRIPTOR BIT(30)
> +#define DCC_RD_MOD_WR_DESCRIPTOR BIT(31)
> +#define DCC_LINK_DESCRIPTOR GENMASK(31, 30)
> +#define DCC_STATUS_MASK GENMASK(1, 0)
> +#define DCC_LOCK_MASK BIT(0)
> +#define DCC_LOOP_OFFSET_MASK BIT(6)
> +#define DCC_TRIGGER_MASK BIT(9)
> +
> +#define DCC_WRITE_MASK BIT(15)
> +#define DCC_WRITE_OFF_MASK GENMASK(7, 0)
> +#define DCC_WRITE_LEN_MASK GENMASK(14, 8)
> +
> +#define DCC_READ_IND 0x00
> +#define DCC_WRITE_IND (BIT(28))
> +
> +#define DCC_AHB_IND 0x00
> +#define DCC_APB_IND BIT(29)
> +
> +#define DCC_MAX_LINK_LIST 8
> +
> +#define DCC_VER_MASK2 GENMASK(5, 0)
> +
> +#define DCC_SRAM_WORD_LENGTH 4
> +
> +#define DCC_RD_MOD_WR_ADDR 0xC105E
> +
> +enum dcc_descriptor_type {
> + DCC_READ_TYPE,
> + DCC_LOOP_TYPE,
> + DCC_READ_WRITE_TYPE,
> + DCC_WRITE_TYPE
> +};
Can you fix the spacing in the macros?
> +static int dcc_add_loop(struct dcc_drvdata *drvdata, unsigned long loop_cnt, int curr_list)
u32 loop_cnt
Lucas
