Re: [PATCH] drm/msm/dpu: add support for 4:2:2 and 4:4:4 planar YCbCr plane formats

[Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>]

On 2/22/2024 3:43 AM, Dmitry Baryshkov wrote:
> The DPU driver provides support for 4:2:0 planar YCbCr plane formats.
> Extend it to also support 4:2:2 and 4:4:4 plat formats.

I checked myself and also internally on this. On sm8250, the DPU planes 
do not support YUV444 and YUV422 (and the corresponding YVU formats).

May I know what was the reference to add these formats to DPU 
considering that even downstream sources didn't add them?

> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
> Full-screen (1080p@60) YV24 gave me underruns on SM8250 until I bumped
> the clock inefficiency factor from 105 to 117. I'm not sure that it is a
> correct way to handle it, so I'm sending this as an RFC. If we agree
> that bumping the .clk_inefficiency_factor is a correct way, I'll send
> v2, including catalog changes.
>
> I had no such issues for the YV16/YU16 formats.

We don't support this too on sm8250. But interesting it worked.

> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c    | 24 ++++++++++++++++++++++++
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c |  4 ++++
>   2 files changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> index e366ab134249..1b763cd95e5a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c
> @@ -475,6 +475,30 @@ static const struct dpu_format dpu_format_map[] = {
>   		C1_B_Cb, C2_R_Cr, C0_G_Y,
>   		false, DPU_CHROMA_420, 1, DPU_FORMAT_FLAG_YUV,
>   		DPU_FETCH_LINEAR, 3),
> +
> +	PLANAR_YUV_FMT(YUV422,
> +		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> +		C2_R_Cr, C1_B_Cb, C0_G_Y,
> +		false, DPU_CHROMA_H2V1, 1, DPU_FORMAT_FLAG_YUV,
> +		DPU_FETCH_LINEAR, 3),
> +
> +	PLANAR_YUV_FMT(YVU422,
> +		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> +		C1_B_Cb, C2_R_Cr, C0_G_Y,
> +		false, DPU_CHROMA_H2V1, 1, DPU_FORMAT_FLAG_YUV,
> +		DPU_FETCH_LINEAR, 3),
> +
> +	PLANAR_YUV_FMT(YUV444,
> +		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> +		C2_R_Cr, C1_B_Cb, C0_G_Y,
> +		false, DPU_CHROMA_RGB, 1, DPU_FORMAT_FLAG_YUV,
> +		DPU_FETCH_LINEAR, 3),
> +
> +	PLANAR_YUV_FMT(YVU444,
> +		0, COLOR_8BIT, COLOR_8BIT, COLOR_8BIT,
> +		C1_B_Cb, C2_R_Cr, C0_G_Y,
> +		false, DPU_CHROMA_RGB, 1, DPU_FORMAT_FLAG_YUV,
> +		DPU_FETCH_LINEAR, 3),
>   };
>   
>   /*
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index ccbee0f40ad7..949c86a44ec7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -195,6 +195,10 @@ static const uint32_t plane_formats_yuv[] = {
>   	DRM_FORMAT_YVYU,
>   	DRM_FORMAT_YUV420,
>   	DRM_FORMAT_YVU420,
> +	DRM_FORMAT_YUV422,
> +	DRM_FORMAT_YVU422,
> +	DRM_FORMAT_YUV444,
> +	DRM_FORMAT_YVU444,
>   };
>   
>   static const u32 rotation_v2_formats[] = {
>
> ---
> base-commit: ffa0c87f172bf7a0132aa960db412f8d63b2f533
> change-id: 20240222-fd-dpu-yv16-yv24-6bf152dfa7f3
>
> Best regards,