On Thu, 8 Feb 2024 16:47:14 +0530 Sneh Shah wrote:
> Serdes phy needs to operate at 2500 mode for 2.5G speed and 1000
> mode for 1G/100M/10M speed.
> Added changes to configure serdes phy and mac based on link speed.
> Changing serdes phy speed involves multiple register writes for
> serdes block. To avoid redundant write operations only update serdes
> phy when new speed is different.
Sounds like 2 separate changes in one patch, please split the
optimization of not writing the registers multiple times and
the 2.5G support.
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> index 31631e3f89d0..6bbdbb7bef44 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> @@ -106,6 +106,7 @@ struct qcom_ethqos {
> struct clk *link_clk;
> struct phy *serdes_phy;
> unsigned int speed;
> + int serdes_speed;
Why signed if speed itself is unsigned?
> /* Enable and restart the Auto-Negotiation */
> if (ane)
> value |= GMAC_AN_CTRL_ANE | GMAC_AN_CTRL_RAN;
> + else
> + value &= ~GMAC_AN_CTRL_ANE;
That looks unrelated. Either a separate patch or please explain in the
commit msg why.
--
pw-bot: cr
