On Tue, 17 Oct 2023 Jason Gunthorpe <jgg@xxxxxxxxxx> wrote:
> Now that the BLOCKED and IDENTITY behaviors are managed with their own
> domains change to the domain_alloc_paging() op.
>
> The check for using_legacy_binding is now redundant,
> arm_smmu_def_domain_type() always returns IOMMU_DOMAIN_IDENTITY for this
> mode, so the core code will never attempt to create a DMA domain in the
> first place.
>
> Since commit a4fdd9762272 ("iommu: Use flush queue capability") the core
> code only passes in IDENTITY/BLOCKED/UNMANAGED/DMA domain types. It will
> not pass in IDENTITY or BLOCKED if the global statics exist, so the test
> for DMA is also redundant now too.
>
> Call arm_smmu_init_domain_context() early if a dev is available.
>
> Signed-off-by: Jason Gunthorpe <jgg@xxxxxxxxxx>
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu.c | 21 +++++++++++++++------
> 1 file changed, 15 insertions(+), 6 deletions(-)
For some reason this patch breaks booting of the APQ8096 Dragonboard820c
(qcom/apq8096-db820c.dts). Dispbling display subsystem (mdss) and venus
devices makes the board boot in most of the cases. Most frequently the
last parts of the log loog in a following way:
arm-smmu b40000.iommu: probing hardware configuration...
arm-smmu b40000.iommu: SMMUv2 with:
arm-smmu b40000.iommu: stage 1 translation
arm-smmu b40000.iommu: address translation ops
arm-smmu b40000.iommu: non-coherent table walk
arm-smmu b40000.iommu: (IDR0.CTTW overridden by FW configuration)
arm-smmu b40000.iommu: stream matching with 2 register groups
arm-smmu b40000.iommu: 2 context banks (0 stage-2 only)
arm-smmu b40000.iommu: Supported page sizes: 0x63315000
arm-smmu b40000.iommu: Stage-1: 48-bit VA -> 36-bit IPA
arm-smmu b40000.iommu: preserved 0 boot mappings
arm-smmu d00000.iommu: probing hardware configuration...
arm-smmu d00000.iommu: SMMUv2 with:
arm-smmu d00000.iommu: stage 1 translation
arm-smmu d00000.iommu: address translation ops
arm-smmu d00000.iommu: non-coherent table walk
arm-smmu d00000.iommu: (IDR0.CTTW overridden by FW configuration)
arm-smmu d00000.iommu: stream matching with 2 register groups
arm-smmu d00000.iommu: 2 context banks (0 stage-2 only)
arm-smmu d00000.iommu: Supported page sizes: 0x63315000
arm-smmu d00000.iommu: Stage-1: 32-bit VA -> 36-bit IPA
arm-smmu d00000.iommu: preserved 0 boot mappings
arm-smmu d40000.iommu: probing hardware configuration...
arm-smmu d40000.iommu: SMMUv2 with:
arm-smmu d40000.iommu: stage 1 translation
arm-smmu d40000.iommu: address translation ops
arm-smmu d40000.iommu: non-coherent table walk
arm-smmu d40000.iommu: (IDR0.CTTW overridden by FW configuration)
arm-smmu d40000.iommu: stream matching with 42 register groups
arm-smmu d40000.iommu: 7 context banks (0 stage-2 only)
arm-smmu d40000.iommu: Supported page sizes: 0x63315000
arm-smmu d40000.iommu: Stage-1: 32-bit VA -> 36-bit IPA
arm-smmu d40000.iommu: preserved 0 boot mappings
arm-smmu da0000.iommu: probing hardware configuration...
arm-smmu da0000.iommu: SMMUv2 with:
arm-smmu da0000.iommu: stage 1 translation
arm-smmu da0000.iommu: address translation ops
arm-smmu da0000.iommu: non-coherent table walk
arm-smmu da0000.iommu: (IDR0.CTTW overridden by FW configuration)
arm-smmu da0000.iommu: stream matching with 4 register groups
arm-smmu da0000.iommu: 2 context banks (0 stage-2 only)
arm-smmu da0000.iommu: Supported page sizes: 0x63315000
arm-smmu da0000.iommu: Stage-1: 32-bit VA -> 36-bit IPA
arm-smmu da0000.iommu: preserved 0 boot mappings
arm-smmu 1600000.iommu: probing hardware configuration...
arm-smmu 1600000.iommu: SMMUv2 with:
arm-smmu 1600000.iommu: stage 1 translation
arm-smmu 1600000.iommu: address translation ops
arm-smmu 1600000.iommu: non-coherent table walk
arm-smmu 1600000.iommu: (IDR0.CTTW overridden by FW configuration)
arm-smmu 1600000.iommu: stream matching with 15 register groups
arm-smmu 1600000.iommu: 12 context banks (0 stage-2 only)
arm-smmu 1600000.iommu: Supported page sizes: 0x63315000
arm-smmu 1600000.iommu: Stage-1: 36-bit VA -> 36-bit IPA
arm-smmu 1600000.iommu: preserved 0 boot mappings
adreno b00000.gpu: Adding to iommu group 0
Bluetooth: hci0: QCA Product ID :0x00000008
Bluetooth: hci0: QCA SOC Version :0x00000044
Bluetooth: hci0: QCA ROM Version :0x00000302
Bluetooth: hci0: QCA Patch Version:0x00000111
Bluetooth: hci0: QCA controller version 0x00440302
platform 9a0000.hdmi-tx: Fixed dependency cycle(s) with /soc@0/display-subsystem@900000/display-controller@901000/ports/port@0/endpoint
Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
spi_qup 7575000.spi: IN:block:16, fifo:64, OUT:block:16, fifo:64
spi_qup 75ba000.spi: IN:block:16, fifo:64, OUT:block:16, fifo:64
phy phy-7411000.phy.5: QUSB2PHY pll lock failed: status reg = 0
phy phy-7411000.phy.5: phy init failed --> -16
dwc3 6a00000.usb: error -EBUSY: failed to initialize core
dwc3: probe of 6a00000.usb failed with error -16
phy phy-7412000.phy.6: QUSB2PHY pll lock failed: status reg = 0
phy phy-7412000.phy.6: phy init failed --> -16
dwc3 7600000.usb: error -EBUSY: failed to initialize core
dwc3: probe of 7600000.usb failed with error -16
i2c_qup 7577000.i2c: using default clock-frequency 100000
i2c_qup 75b5000.i2c: using default clock-frequency 100000
sdhci_msm 74a4900.mmc: Got CD GPIO
scsi host0: ufshcd
ufshcd-qcom 624000.ufshc: ufs_qcom_host_reset: reset control not set
remoteproc remoteproc0: 2080000.remoteproc is available
remoteproc remoteproc1: 9300000.remoteproc is available
mmc0: SDHCI controller on 74a4900.mmc [74a4900.mmc] using ADMA 64-bit
qcom-pcie 600000.pcie: host bridge /soc@0/bus@0/pcie@600000 ranges:
qcom-pcie 608000.pcie: supply vddpe-3v3 not found, using dummy regulator
[ The board resets to the bootloader ]
