On Thu, 8 Feb 2024 at 08:29, Taniya Das <quic_tdas@xxxxxxxxxxx> wrote:
>
> The GDSC default values are being updated and they can cause issues
> in the GDSC FSM state.
It reads as if new values can cause issues with the FSM.
> While at it also update the force mem core
> for UFS ICE clock.
Separate patch, please.
>
> Fixes: fae7617bb142 ("clk: qcom: Add video clock controller driver for SC7280")
> Fixes: 1daec8cfebc2 ("clk: qcom: camcc: Add camera clock controller driver for SC7280")
> Fixes: a3cc092196ef ("clk: qcom: Add Global Clock controller (GCC) driver for SC7280")
> Fixes: 3e0f01d6c7e7 ("clk: qcom: Add graphics clock controller driver for SC7280")
> Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> ---
> drivers/clk/qcom/camcc-sc7280.c | 19 +++++++++++++++++++
> drivers/clk/qcom/gcc-sc7280.c | 13 +++++++++++++
> drivers/clk/qcom/gpucc-sc7280.c | 7 +++++++
> drivers/clk/qcom/videocc-sc7280.c | 7 +++++++
> 4 files changed, 46 insertions(+)
>
> diff --git a/drivers/clk/qcom/camcc-sc7280.c b/drivers/clk/qcom/camcc-sc7280.c
> index 49f046ea857c..4849b0e8c846 100644
> --- a/drivers/clk/qcom/camcc-sc7280.c
> +++ b/drivers/clk/qcom/camcc-sc7280.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #include <linux/clk-provider.h>
> @@ -2247,6 +2248,9 @@ static struct clk_branch cam_cc_sleep_clk = {
>
> static struct gdsc cam_cc_titan_top_gdsc = {
> .gdscr = 0xc194,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "cam_cc_titan_top_gdsc",
> },
> @@ -2256,6 +2260,9 @@ static struct gdsc cam_cc_titan_top_gdsc = {
>
> static struct gdsc cam_cc_bps_gdsc = {
> .gdscr = 0x7004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "cam_cc_bps_gdsc",
> },
> @@ -2265,6 +2272,9 @@ static struct gdsc cam_cc_bps_gdsc = {
>
> static struct gdsc cam_cc_ife_0_gdsc = {
> .gdscr = 0xa004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "cam_cc_ife_0_gdsc",
> },
> @@ -2274,6 +2284,9 @@ static struct gdsc cam_cc_ife_0_gdsc = {
>
> static struct gdsc cam_cc_ife_1_gdsc = {
> .gdscr = 0xb004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "cam_cc_ife_1_gdsc",
> },
> @@ -2283,6 +2296,9 @@ static struct gdsc cam_cc_ife_1_gdsc = {
>
> static struct gdsc cam_cc_ife_2_gdsc = {
> .gdscr = 0xb070,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "cam_cc_ife_2_gdsc",
> },
> @@ -2292,6 +2308,9 @@ static struct gdsc cam_cc_ife_2_gdsc = {
>
> static struct gdsc cam_cc_ipe_0_gdsc = {
> .gdscr = 0x8004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "cam_cc_ipe_0_gdsc",
> },
> diff --git a/drivers/clk/qcom/gcc-sc7280.c b/drivers/clk/qcom/gcc-sc7280.c
> index 2b661df5de26..5f3bfb6f4fbb 100644
> --- a/drivers/clk/qcom/gcc-sc7280.c
> +++ b/drivers/clk/qcom/gcc-sc7280.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #include <linux/clk-provider.h>
> @@ -3094,6 +3095,9 @@ static struct clk_branch gcc_wpss_rscp_clk = {
>
> static struct gdsc gcc_pcie_0_gdsc = {
> .gdscr = 0x6b004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "gcc_pcie_0_gdsc",
> },
> @@ -3112,6 +3116,9 @@ static struct gdsc gcc_pcie_1_gdsc = {
>
> static struct gdsc gcc_ufs_phy_gdsc = {
> .gdscr = 0x77004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "gcc_ufs_phy_gdsc",
> },
> @@ -3121,6 +3128,9 @@ static struct gdsc gcc_ufs_phy_gdsc = {
>
> static struct gdsc gcc_usb30_prim_gdsc = {
> .gdscr = 0xf004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0xf,
> .pd = {
> .name = "gcc_usb30_prim_gdsc",
> },
> @@ -3467,6 +3477,9 @@ static int gcc_sc7280_probe(struct platform_device *pdev)
> regmap_update_bits(regmap, 0x71004, BIT(0), BIT(0));
> regmap_update_bits(regmap, 0x7100C, BIT(13), BIT(13));
>
> + /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
> + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true);
> +
> ret = qcom_cc_register_rcg_dfs(regmap, gcc_dfs_clocks,
> ARRAY_SIZE(gcc_dfs_clocks));
> if (ret)
> diff --git a/drivers/clk/qcom/gpucc-sc7280.c b/drivers/clk/qcom/gpucc-sc7280.c
> index 1490cd45a654..0eea4cf7954d 100644
> --- a/drivers/clk/qcom/gpucc-sc7280.c
> +++ b/drivers/clk/qcom/gpucc-sc7280.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #include <linux/clk-provider.h>
> @@ -379,6 +380,9 @@ static struct clk_branch gpu_cc_sleep_clk = {
>
> static struct gdsc cx_gdsc = {
> .gdscr = 0x106c,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0x2,
> .gds_hw_ctrl = 0x1540,
> .pd = {
> .name = "cx_gdsc",
> @@ -389,6 +393,9 @@ static struct gdsc cx_gdsc = {
>
> static struct gdsc gx_gdsc = {
> .gdscr = 0x100c,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0x2,
> .clamp_io_ctrl = 0x1508,
> .pd = {
> .name = "gx_gdsc",
> diff --git a/drivers/clk/qcom/videocc-sc7280.c b/drivers/clk/qcom/videocc-sc7280.c
> index 615695d82319..b07895c459e8 100644
> --- a/drivers/clk/qcom/videocc-sc7280.c
> +++ b/drivers/clk/qcom/videocc-sc7280.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> * Copyright (c) 2021, The Linux Foundation. All rights reserved.
> + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
> */
>
> #include <linux/clk-provider.h>
> @@ -232,6 +233,9 @@ static struct clk_branch video_cc_venus_ahb_clk = {
>
> static struct gdsc mvs0_gdsc = {
> .gdscr = 0x3004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0x6,
> .pd = {
> .name = "mvs0_gdsc",
> },
> @@ -241,6 +245,9 @@ static struct gdsc mvs0_gdsc = {
>
> static struct gdsc mvsc_gdsc = {
> .gdscr = 0x2004,
> + .en_rest_wait_val = 0x2,
> + .en_few_wait_val = 0x2,
> + .clk_dis_wait_val = 0x6,
> .pd = {
> .name = "mvsc_gdsc",
> },
> --
> 2.17.1
>
>
--
With best wishes
Dmitry
