On Thu, 25 Jan 2024 17:55:04 +0100, Neil Armstrong wrote:
> Both PCIe0 and PCIe1 controllers are capable of signalling the MSIs
> received from endpoint devices to the CPU using GIC-ITS MSI controller.
> Add support for it.
>
> The GIC-ITS MSI implementation provides an advantage over internal MSI
> implementation using Locality-specific Peripheral Interrupts (LPI) that
> would allow MSIs to be targeted for each CPU core.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: qcom: sm8650: Use GIC-ITS for PCIe0 and PCIe1
commit: a33a532b3b1ecd6a64f6280d29d19f3ed6e31a92
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
