On 24/01/2024 08:36, Manivannan Sadhasivam wrote: > On some platforms, PHY block requires PCIE_PHY_AUX_CLK to be used when the > PCIe link enters L1SS state. On those platforms, a dedicated > PCIE_PHY_AUX_CLK is available from GCC. Other than this, the PHY block > doesn't require any other "aux" clock, including PCIE_AUX_CLK which only > required by the PCIe controller. > > Historically, the DTs of the platforms requiring "aux" clock passed > PCIE_PHY_AUX_CLK as "aux" clock. But over the period of time, platforms > that do not require this dedicated "aux" clock mistakenly started passing > the PCIE_AUX_CLK as the "aux" clock. More recently, SA8775P platform passed > both "aux" (PCIE_AUX_CLK) and "phy_aux" (PCIE_PHY_AUX_CLK) clocks. > > So to clean up this mess, let's remove the newly introduced "phy_aux" clock > and just use "aux" clock to supply PCIE_PHY_AUX_CLK for platforms that > require it. For the platforms that do not require a dedicated "aux" clock, > the clock is removed from DT. > > While at it, let's also define "qcom,sc7280-qmp-pcie-phy" compatible for > SC7280 SoC which was earlier using the compatible > "qcom,sm8250-qmp-gen3x2-pcie-phy" as the clock requirement has changed and > also restructure the "clock-names" property for the affected platforms. > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
