Re: [PATCH 13/17] drm/msm/dp: enable SDP and SDE periph flush update

[Paloma Arellano <quic_parellan@xxxxxxxxxxx>]

On 1/25/2024 1:50 PM, Dmitry Baryshkov wrote:
> On 25/01/2024 21:38, Paloma Arellano wrote:
> > DP controller can be setup to operate in either SDP update flush mode or
> > peripheral flush mode based on the DP controller hardware version.
> >
> > Starting in DP v1.2, the hardware documents require the use of
> > peripheral flush mode for SDP packets such as PPS OR VSC SDP packets.
> >
> > In-line with this guidance, lets program the DP controller to use
> > peripheral flush mode starting DP v1.2
> >
> > Signed-off-by: Paloma Arellano <quic_parellan@xxxxxxxxxxx>
> > ---
> >   drivers/gpu/drm/msm/dp/dp_catalog.c | 18 ++++++++++++++++++
> >   drivers/gpu/drm/msm/dp/dp_catalog.h |  1 +
> >   drivers/gpu/drm/msm/dp/dp_ctrl.c    |  1 +
> >   drivers/gpu/drm/msm/dp/dp_reg.h     |  2 ++
> >   4 files changed, 22 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c 
> > b/drivers/gpu/drm/msm/dp/dp_catalog.c
> > index 7e4c68be23e56..b43083b9c2df6 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_catalog.c
> > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c
> > @@ -446,6 +446,24 @@ void dp_catalog_ctrl_config_misc(struct 
> > dp_catalog *dp_catalog,
> >       dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val);
> >   }
> >   +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog)
> > +{
> > +    u32 mainlink_ctrl;
> > +    u16 major = 0, minor = 0;
> > +    struct dp_catalog_private *catalog = container_of(dp_catalog,
> > +                struct dp_catalog_private, dp_catalog);
> > +
> > +    mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL);
> > +
> > +    dp_catalog_hw_revision(dp_catalog, &major, &minor);
> > +    if (major >= 1 && minor >= 2)
>
> if (major > 1 || (major == 1 && minor >= 2))
>
> As a check, which of the values should be written for maj.min = 2.1?
Ack. My mistake
> > +        mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE;
> > +    else
> > +        mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP;
> > +
> > +    dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl);
> > +}
> > +
> >   void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog,
> >                       u32 rate, u32 stream_rate_khz,
> >                       bool fixed_nvid, bool is_ycbcr_420)
> > diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h 
> > b/drivers/gpu/drm/msm/dp/dp_catalog.h
> > index 6b757249c0698..1d57988aa6689 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_catalog.h
> > +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h
> > @@ -169,6 +169,7 @@ void dp_catalog_ctrl_config_ctrl(struct 
> > dp_catalog *dp_catalog, u32 config);
> >   void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog);
> >   void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, 
> > bool enable);
> >   void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog 
> > *dp_catalog, bool enable);
> > +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog);
> >   void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 
> > cc, u32 tb);
> >   void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 
> > rate,
> >                   u32 stream_rate_khz, bool fixed_nvid, bool 
> > is_ycbcr_420);
> > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c 
> > b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> > index ddd92a63d5a67..c375b36f53ce1 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c
> > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c
> > @@ -170,6 +170,7 @@ static void 
> > dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl)
> >         dp_catalog_ctrl_lane_mapping(ctrl->catalog);
> >       dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true);
> > +    dp_catalog_setup_peripheral_flush(ctrl->catalog);
> >         dp_ctrl_config_ctrl(ctrl);
> >   diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h 
> > b/drivers/gpu/drm/msm/dp/dp_reg.h
> > index 756ddf85b1e81..05a1009d2f678 100644
> > --- a/drivers/gpu/drm/msm/dp/dp_reg.h
> > +++ b/drivers/gpu/drm/msm/dp/dp_reg.h
> > @@ -102,6 +102,8 @@
> >   #define DP_MAINLINK_CTRL_ENABLE            (0x00000001)
> >   #define DP_MAINLINK_CTRL_RESET            (0x00000002)
> >   #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER    (0x00000010)
> > +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP    (0x00800000)
> > +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE (0x01800000)
> >   #define DP_MAINLINK_FB_BOUNDARY_SEL        (0x02000000)
> >     #define REG_DP_STATE_CTRL            (0x00000004)