On Thu, 25 Jan 2024 at 23:26, Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> wrote: > > On 25/01/2024 21:38, Paloma Arellano wrote: > > INTF_CONFIG2 register cannot have widebus enabled when DP format is > > YUV420. Therefore, program the INTF to send 1 ppc. > > I think this is handled in the DP driver, where we disallow wide bus for > YUV 4:2:0 modes. Maybe this needs some explanation from my side: I think it will be better to have separate conditionals for setting HCTL_EN and for DATABUS_WIDEN. > > > > > Signed-off-by: Paloma Arellano <quic_parellan@xxxxxxxxxxx> > > --- > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > index 6bba531d6dc41..bfb93f02fe7c1 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > > @@ -168,7 +168,9 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, > > * video timing. It is recommended to enable it for all cases, except > > * if compression is enabled in 1 pixel per clock mode > > */ > > - if (p->wide_bus_en) > > + if (dp_intf && fmt->base.pixel_format == DRM_FORMAT_YUV420) > > + intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN; > > + else if (p->wide_bus_en) > > intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; > > > > data_width = p->width; > > -- > With best wishes > Dmitry > -- With best wishes Dmitry
