PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy node.
This also warrants a new compatible as the clocks differ between SC7280 and
SM8250.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 83b5b76ba179..00fa14777417 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -2238,15 +2238,13 @@ pcie1: pcie@1c08000 {
};
pcie1_phy: phy@1c0e000 {
- compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
+ compatible = "qcom,sc7280-qmp-pcie-phy";
reg = <0 0x01c0e000 0 0x1000>;
- clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
- <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
+ clocks = <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_EN>,
<&gcc GCC_PCIE1_PHY_RCHNG_CLK>,
<&gcc GCC_PCIE_1_PIPE_CLK>;
- clock-names = "aux",
- "cfg_ahb",
+ clock-names = "cfg_ahb",
"ref",
"refgen",
"pipe";
--
2.25.1
