PCIe PHY hw doesn't require PCIE_AUX_CLK for functioning. This clock is
only required by the PCIe controller. Hence drop it from pcie_phy nodes.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index cf295bed3299..6ae6833e8969 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -201,11 +201,9 @@ pcie_qmp0: phy@84000 {
compatible = "qcom,ipq8074-qmp-gen3-pcie-phy";
reg = <0x00084000 0x1000>;
- clocks = <&gcc GCC_PCIE0_AUX_CLK>,
- <&gcc GCC_PCIE0_AHB_CLK>,
+ clocks = <&gcc GCC_PCIE0_AHB_CLK>,
<&gcc GCC_PCIE0_PIPE_CLK>;
- clock-names = "aux",
- "cfg_ahb",
+ clock-names = "cfg_ahb",
"pipe";
clock-output-names = "pcie20_phy0_pipe_clk";
@@ -224,11 +222,9 @@ pcie_qmp1: phy@8e000 {
compatible = "qcom,ipq8074-qmp-pcie-phy";
reg = <0x0008e000 0x1000>;
- clocks = <&gcc GCC_PCIE1_AUX_CLK>,
- <&gcc GCC_PCIE1_AHB_CLK>,
+ clocks = <&gcc GCC_PCIE1_AHB_CLK>,
<&gcc GCC_PCIE1_PIPE_CLK>;
- clock-names = "aux",
- "cfg_ahb",
+ clock-names = "cfg_ahb",
"pipe";
clock-output-names = "pcie20_phy1_pipe_clk";
--
2.25.1
