On Tue, Jan 23, 2024 at 10:36:14PM +0530, Manivannan Sadhasivam wrote: > On Mon, Jan 22, 2024 at 06:36:51PM +0100, Johan Hovold wrote: > Ok. I tested by enabling the PHY clocks during qmp_pcie_clk_init() without > PCIE_GDSC. It worked for one instance of the PHY which doesn't have > PCIE_PHY_AUX_CLK, but for the PHY instance with this clock, I saw the same "clk > stuck" issue. Then checking the internal documentation revealed that this clock > needs PCIE_GDSC to become functional >.< > > So to conclude, PCIE_AUX_CLK belongs to the controller and it needs GDSC. And > PCIE_PHY_AUX_CLK belongs to the PHY and it also needs GDSC. > > I will just submit a series to remove the PCIE_AUX_CLK from PHY nodes. Then > in another series, I'll remove the GDSC for PHY instances that do not require > PCIE_PHY_AUX_CLK. Sounds good, thanks. Johan
