On 23/01/2024 16:34, Bjorn Andersson wrote: > On Tue, Jan 23, 2024 at 10:22:33AM +0100, Bartosz Golaszewski wrote: >> On Tue, Jan 23, 2024 at 5:47 AM Bjorn Andersson <andersson@xxxxxxxxxx> wrote: >>> >>> On Mon, Jan 22, 2024 at 07:21:58PM +0100, Bartosz Golaszewski wrote: >>>> From: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx> >>>> >>>> I'm limiting the audience of this compared to the PCI power sequencing >>>> series as I wanted to run the DT part by the maintainers before I commit >>>> to a doomed effort. >>>> >>> >>> With linux-arm-msm and deviectree in there, you have a fairly big >>> limited audience... I think if anything, your proposal is doomed by the >>> lack of a proper commit message describing what this is. >>> >> >> By limiting I meant compared to the PCI power sequencing series but >> you're right, I should have linked that series in here. In any case - >> this is not intended for upstream, I literally wanted input on whether >> this representation is correct before I send a PoC of the pwrseq >> subsystem using it. >> >>> Below you'll find some questions/feedback based on our previous >>> discussions on the topic, although I'm not able to understand the >>> motivations behind what you propose - or even fully what it is that >>> you're proposing. >>> >>>> Here is the DT representation of the QCA6390's PMU with its inputs and >>>> outputs. If I were to implement the pwrseq framework that would be able >>>> to assign the relevant pwrseq data to the consumer based on the actual >>>> regulators and not abstract bt-pwrseq or wlan-pwrseq properties - would >>>> that fly with you? >>>> >>> >>> Why do you need to make up this intermediate/fake "PMU" thing? The >>> regulators are reference counted already. >>> >> >> Dmitry insists that for QCA6490 we *do* need to implement a proper >> power sequencing with delays between enabling WLAN and BT GPIOs. >> >> See: https://lore.kernel.org/netdev/CAA8EJpqyK=pkjEofWV595tp29vjkCeWKYr-KOJh_hBiBbkVBew@xxxxxxxxxxxxxx/ >> > > I had not seen that comment before, would have been excellent to include > in your "problem description". > >> Even though the regulators are reference counted, this is not enough. >> Dmitry tried to implement a power sequencing framework some time ago >> but the main complaint was that explicit properties like bt-pwrseq are >> not a right fit for DT as they don't represent hardware. We still need >> to centralize the control over the shared resources though but what I >> want to propose is doing that with a more realistic representation of >> HW and just reusing phandle connections between DT nodes to retrieve >> the correct pwrseq struct in the driver. But this is implementation >> detail and before I want to clear the HW representation with DT >> maintainers. >> > > In my view Dmitry had at least one proposal, that was rejected, where he > represented the qca6390 package as a thing in DeviceTree. > >> Dmitry is also correct in pointing out that It's also simply an >> incorrect representation of what is on the board as the PMU is a >> discrete module, has its inputs and outputs, even though they're >> inside the package. >> > > I'm not sure what you're trying to say here. There's no "PMU module" on > the board, it's a block within the QCA6390. But perhaps that's what > you're also saying? While the board does not have, the board schematics have it, e.g. RB5. Also QCA datasheet (at least the one on RB5) describes relationships between the external supplies, feeding PMU in my understanding, and internal supplies, coming from PMU to specific blocks. Best regards, Krzysztof
