On 1/16/24 16:04, Bibek Kumar Patro wrote:
Currently in Qualcomm SoCs the default prefetch is set to 1 which allows
the TLB to fetch just the next page table. MMU-500 features ACTLR
register which is implementation defined and is used for Qualcomm SoCs
to have a custom prefetch setting enabling TLB to prefetch the next set
of page tables accordingly allowing for faster translations.
ACTLR value is unique for each SMR (Stream matching register) and stored
in a pre-populated table. This value is set to the register during
context bank initialisation.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
Since it's your idea with Dmitry's review suggestions, I don't think
this tag makes sense.
It's normally used for situations like:
Colleague X: "Hey Bibek, I noticed x broke on y, can you fix it?"
"Sure!" <proceeds to make a commit with suggested-by Colleague X>
Just a nit below:
+struct actlr_config {
+ u16 sid;
+ u16 mask;
+ u32 actlr;
+};
This, can go here, in the header:
+struct actlr_config;
+
+struct actlr_variant {
+ const resource_size_t io_start;
+ const struct actlr_config * const actlrcfg;
+ const size_t num_actlrcfg;
+};
+
Otherwise, this looks good!
Konrad
