On Wed, 17 Jan 2024 at 19:37, Sibi Sankar <quic_sibis@xxxxxxxxxxx> wrote:
>
> Enable LLCC/DDR dvfs through the Qualcomm's SCMI vendor protocol.
Could you please post DT bindings?
>
> Signed-off-by: Sibi Sankar <quic_sibis@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 48 ++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 6856a206f7fc..3dc6f32fbb4c 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -329,6 +329,54 @@ scmi_dvfs: protocol@13 {
> reg = <0x13>;
> #clock-cells = <1>;
> };
> +
> + scmi_vendor: protocol@80 {
> + reg = <0x80>;
> +
> + memlat {
This doesn't look like a generic node name.
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + memory@0 {
> + reg = <0x0>; /* Memory Type DDR */
> + freq-table-khz = <200000 4224000>;
> +
> + monitor-0 {
> + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>;
> + qcom,cpufreq-memfreq-tbl = < 999000 547000 >,
> + < 1440000 768000 >,
> + < 1671000 1555000 >,
> + < 2189000 2092000 >,
> + < 2156000 3187000 >,
> + < 3860000 4224000 >;
These tables should be rewritten as OPP tables.
> + };
> +
> + monitor-1 {
> + qcom,compute-mon;
> + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>;
> + qcom,cpufreq-memfreq-tbl = < 1440000 200000 >,
> + < 2189000 768000 >,
> + < 2156000 1555000 >,
> + < 3860000 2092000 >;
> + };
> + };
> +
> + memory@1 {
> + reg = <0x1>; /* Memory Type LLCC */
> + freq-table-khz = <300000 1067000>;
> +
> + monitor-0 {
> + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5 &CPU6 &CPU7 &CPU8 &CPU9 &CPU10 &CPU11>;
> + qcom,cpufreq-memfreq-tbl = < 999000 300000 >,
> + < 1440000 466000 >,
> + < 1671000 600000 >,
> + < 2189000 806000 >,
> + < 2156000 933000 >,
> + < 3860000 1066000 >;
> + };
> + };
> + };
> + };
> };
> };
>
> --
> 2.34.1
>
>
--
With best wishes
Dmitry
