On 1/8/2024 12:50 PM, Brian Masney wrote:
> On Mon, Jan 08, 2024 at 11:44:35PM +0530, Shazad Hussain wrote:
>> I can see that gcc_ufs_phy_ice_core_clk needs the gcc_ufs_phy_gdsc to be
>> enabled before this particular clk is enabled. But that required
>> power-domain I do not see in the ice DT node. That can cause this
>> problem.
>
> Thank you! I'll work on and post a patch set as I find free time over
> the next week or two.
I think I observe the same issue on sm8650. Symptoms seem to be same as
you've described. I'll test out the following diff and see if things
seem more reliable:
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index fd4f9dac48a3..c9ea50834dc9 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2526,6 +2526,7 @@ ice: crypto@1d88000 {
"qcom,inline-crypto-engine";
reg = <0 0x01d88000 0 0x8000>;
+ power-domains = <&gcc UFS_PHY_GDSC>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
};
If yes, I can post a patch for sm8650 if no else has yet.
