Hi Andrew,
On 05.01.2024 15:52, Andrew Lunn wrote:
On Fri, Jan 05, 2024 at 04:48:31AM +0200, Sergey Ryazanov wrote:
Hi Luo,
thank you for explaining the case in such details. I also have checked the
related DTSs in the Linaro repository to be more familiar with the I/O mem
layout. Specifically I checked these two, hope they are relevant to the
discussion:
https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r3/arch/arm64/boot/dts/qcom/ipq5332.dtsi
https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/blob/NHSS.QSDK.12.4.r3/arch/arm64/boot/dts/qcom/ipq9574.dtsi
Please find my comments below.
Hi Sergey
There is a second thread going on, focused around the quad PHY. See:
https://lore.kernel.org/netdev/60b9081c-76fa-4122-b7ae-5c3dcf7229f9@xxxxxxx/
Yeah. I had read your discussion yesterday before coming back to this
clock discussion. It is a monster chip and looks like you have a hard
time figuring out how it works and looking for a good code/DT model.
Since it is very hard to get consistent information out of Luo, he has
annoyed nearly all the PHY maintainers and all the DT maintainers, i'm
going back to baby steps, focusing on just the quad pure PHY, and
trying to get that understood and correctly described in DT.
However, does Linaro have any interest in just taking over this work,
or mentoring Luo?
I should clarify here a bit. I found this discussion while looking for a
way to port one open source firmware to my router based on previous IPQ
generation. And since I am a bit familiar with this chip family, I chose
to put my 2c to make implementation discussion more structured. Long
story short, I have no idea about Linaro's plans :)
If I am allowed to speak, the chosen baby steps approach to focus on
pure PHY seems to be the only sane method in that case. Considering
Alex's promise, we can assume that the next release will support this PHY.
--
Sergey
