On 03/01/2024 20:20, Konrad Dybcio wrote:
> SDM845 downstream uses non-default values for GDSC internal waits.
> Program them accordingly to avoid surprises.
>
> Fixes: 81351776c9fb ("clk: qcom: Add display clock controller driver for SDM845")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
This doesn't break anything, but I'm not exactly sure what it fixes :P
Tested-by: Caleb Connolly <caleb.connolly@xxxxxxxxxx> # OnePlus 6
> ---
> drivers/clk/qcom/dispcc-sdm845.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/qcom/dispcc-sdm845.c b/drivers/clk/qcom/dispcc-sdm845.c
> index 735adfefc379..e792e0b130d3 100644
> --- a/drivers/clk/qcom/dispcc-sdm845.c
> +++ b/drivers/clk/qcom/dispcc-sdm845.c
> @@ -759,6 +759,8 @@ static struct clk_branch disp_cc_mdss_vsync_clk = {
>
> static struct gdsc mdss_gdsc = {
> .gdscr = 0x3000,
> + .en_few_wait_val = 0x6,
> + .en_rest_wait_val = 0x5,
> .pd = {
> .name = "mdss_gdsc",
> },
>
> ---
> base-commit: 0fef202ac2f8e6d9ad21aead648278f1226b9053
> change-id: 20240103-topic-845gdsc-bcd9d549f153
>
> Best regards,
--
// Caleb (they/them)
