On Wed, Dec 27, 2023 at 11:17:21PM +0100, Konrad Dybcio wrote: > To ensure write completion, read the PARF_LTSSM register after setting > the LTSSM enable bit before polling for "link up". > > Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> I'd consider this as a bug since if the LTSSM write gets cached in Write Buffer, then the polling time becomes wrong in dw_pcie_wait_for_link(), leading to false link_up failure. Although both of the write/read (LTSSM in qcom_pcie_2_3_2_ltssm_enable(), and PCI_EXP_LNKSTA in qcom_pcie_link_up()) belong to PCIe domain, they belong to different regions (PARF, DBI). So I'm not sure we can safely ignore the write completion issue. So, Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx> - Mani > --- > drivers/pci/controller/dwc/pcie-qcom.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index a02dc197c495..3d77269e70da 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -540,6 +540,7 @@ static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) > val = readl(pcie->parf + PARF_LTSSM); > val |= LTSSM_EN; > writel(val, pcie->parf + PARF_LTSSM); > + readl(pcie->parf + PARF_LTSSM); > } > > static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) > > -- > 2.43.0 > -- மணிவண்ணன் சதாசிவம்
