On 29.12.2023 12:24, Johan Hovold wrote: > On Wed, Dec 27, 2023 at 11:28:26PM +0100, Konrad Dybcio wrote: >> The PCIe GDSCs are only related to the RCs. The PCIe PHYs on the other >> hand, are powered by VDD_MX and their specific VDDA_PHY/PLL regulators. > > No, that does not seem to be entirely correct. I added the power-domains > here precisely because they were needed to enable the PHYs. > > This is something I stumbled over when trying to figure out how to > add support for the second lane pair (i.e. four-lane mode), and I just > went back and confirmed that this is still the case. > > If you try to enable one of these PHYs without the corresponding GDSC > being enabled, you end up with: > > [ 37.709324] ------------[ cut here ]------------ > [ 37.718196] gcc_pcie_3b_aux_clk status stuck at 'off' > [ 37.718205] WARNING: CPU: 4 PID: 482 at drivers/clk/qcom/clk-branch.c:86 clk_branch_wait+0x144/0x15c > > Now, you may or may not want to describe the above in the devicetree, > but this makes it sound like you're trying to work around an issue with > the current Linux implementation. Could you please recheck this with patch 1 from [1] applied? Konrad [1] https://lore.kernel.org/linux-arm-msm/20231227-topic-8280_pcie-v1-1-095491baf9e4@xxxxxxxxxx/T/#u
