With the necessary support in place for supplying VDD_GFX from the MAX20411 regulator, enable the GPU clock controller, GMU, Adreno SMMU and the GPU on the SA8295P ADP. Signed-off-by: Bjorn Andersson <quic_bjorande@xxxxxxxxxxx> --- arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts index 14327c697116..304c8d79bd31 100644 --- a/arch/arm64/boot/dts/qcom/sa8295p-adp.dts +++ b/arch/arm64/boot/dts/qcom/sa8295p-adp.dts @@ -108,6 +108,13 @@ edp3_connector_in: endpoint { }; }; }; + + reserved-memory { + gpu_mem: gpu-mem@8bf00000 { + reg = <0 0x8bf00000 0 0x2000>; + no-map; + }; + }; }; &apps_rsc { @@ -286,6 +293,28 @@ vdd_gfx: regulator@39 { }; }; +&gpucc { + vdd-gfx-supply = <&vdd_gfx>; + status = "okay"; +}; + +&gmu { + status = "okay"; +}; + +&gpu { + status = "okay"; + + zap-shader { + memory-region = <&gpu_mem>; + firmware-name = "qcom/sa8295p/a690_zap.mbn"; + }; +}; + +&gpu_smmu { + status = "okay"; +}; + &mdss0 { status = "okay"; }; -- 2.25.1