On Wed, 06 Dec 2023 21:02:51 +0530, Mukesh Ojha wrote:
> Commit c14e64b46944 ("soc: qcom: llcc: Support chipsets that can
> write to llcc") add the support for chipset where capacity based
> allocation and retention through power collapse can be programmed
> based on content of SCT table mentioned in the llcc driver where
> the target like sdm845 where the entire programming related to it
> is controlled in firmware. However, the commit introduces a bug
> where capacity/retention register get overwritten each time it
> gets programmed for each slice and that results in misconfiguration
> of the register based on SCT table and that is not expected
> behaviour instead it should be read modify write to retain the
> configuration of other slices.
>
> [...]
Applied, thanks!
[1/1] soc: qcom: llcc: Fix dis_cap_alloc and retain_on_pc configuration
commit: eed6e57e9f3e2beac37563eb6a0129549daa330e
Best regards,
--
Bjorn Andersson <andersson@xxxxxxxxxx>
