On 14/12/2023 07:28, Praveenkumar I wrote: > Add support for the PCIe controller on the Qualcomm > IPQ5332 SoC to the bindings. > > Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx> > --- > .../devicetree/bindings/pci/qcom,pcie.yaml | 36 +++++++++++++++++++ > 1 file changed, 36 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index eadba38171e1..af5e67d2a984 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -21,6 +21,7 @@ properties: > - qcom,pcie-apq8064 > - qcom,pcie-apq8084 > - qcom,pcie-ipq4019 > + - qcom,pcie-ipq5332 > - qcom,pcie-ipq6018 > - qcom,pcie-ipq8064 > - qcom,pcie-ipq8064-v2 > @@ -170,6 +171,7 @@ allOf: > compatible: > contains: > enum: > + - qcom,pcie-ipq5332 > - qcom,pcie-ipq6018 > - qcom,pcie-ipq8074-gen3 > then: > @@ -332,6 +334,39 @@ allOf: > - const: ahb # AHB reset > - const: phy_ahb # PHY AHB reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-ipq5332 > + then: > + properties: > + clocks: > + minItems: 6 > + maxItems: 6 > + clock-names: > + items: > + - const: ahb # AHB clock > + - const: aux # Auxiliary clock > + - const: axi_m # AXI Master clock > + - const: axi_s # AXI Slave clock > + - const: axi_bridge # AXI bridge clock > + - const: rchng > + resets: > + minItems: 8 > + maxItems: 8 > + reset-names: > + items: > + - const: pipe # PIPE reset No sleep reset? Otherwise it looks like some existing entry, so you should use the same order of resets. Best regards, Krzysztof
