Convert register read/write for sha via BAM/DMA.
with this change all the crypto register configuration
will be done via BAM/DMA. This change will prepare command
descriptor for all register and write it once.
Signed-off-by: Md Sadre Alam <quic_mdalam@xxxxxxxxxxx>
---
drivers/crypto/qce/common.c | 26 +++++++++++++++++---------
drivers/crypto/qce/sha.c | 12 ++++++++++++
2 files changed, 29 insertions(+), 9 deletions(-)
diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c
index d1da6b1938f3..d485762a3fdc 100644
--- a/drivers/crypto/qce/common.c
+++ b/drivers/crypto/qce/common.c
@@ -157,17 +157,19 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req)
__be32 mackey[QCE_SHA_HMAC_KEY_SIZE / sizeof(__be32)] = {0};
u32 auth_cfg = 0, config;
unsigned int iv_words;
+ int ret;
/* if not the last, the size has to be on the block boundary */
if (!rctx->last_blk && req->nbytes % blocksize)
return -EINVAL;
+ qce_clear_bam_transaction(qce);
qce_setup_config(qce);
if (IS_CMAC(rctx->flags)) {
- qce_write(qce, REG_AUTH_SEG_CFG, 0);
- qce_write(qce, REG_ENCR_SEG_CFG, 0);
- qce_write(qce, REG_ENCR_SEG_SIZE, 0);
+ qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, 0, 1);
+ qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, 0, 1);
+ qce_write_reg_dma(qce, REG_ENCR_SEG_SIZE, 0, 1);
qce_clear_array(qce, REG_AUTH_IV0, 16);
qce_clear_array(qce, REG_AUTH_KEY0, 16);
qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
@@ -213,18 +215,24 @@ static int qce_setup_regs_ahash(struct crypto_async_request *async_req)
auth_cfg &= ~BIT(AUTH_FIRST_SHIFT);
go_proc:
- qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
- qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);
- qce_write(qce, REG_AUTH_SEG_START, 0);
- qce_write(qce, REG_ENCR_SEG_CFG, 0);
- qce_write(qce, REG_SEG_SIZE, req->nbytes);
+ qce_write_reg_dma(qce, REG_AUTH_SEG_CFG, auth_cfg, 1);
+ qce_write_reg_dma(qce, REG_AUTH_SEG_SIZE, req->nbytes, 1);
+ qce_write_reg_dma(qce, REG_AUTH_SEG_START, 0, 1);
+ qce_write_reg_dma(qce, REG_ENCR_SEG_CFG, 0, 1);
+ qce_write_reg_dma(qce, REG_SEG_SIZE, req->nbytes, 1);
/* get little endianness */
config = qce_config_reg(qce, 1);
- qce_write(qce, REG_CONFIG, config);
+ qce_write_reg_dma(qce, REG_CONFIG, config, 1);
qce_crypto_go(qce, true);
+ ret = qce_submit_cmd_desc(qce, 0);
+ if (ret) {
+ dev_err(qce->dev, "Error in sha cmd descriptor\n");
+ return ret;
+ }
+
return 0;
}
#endif
diff --git a/drivers/crypto/qce/sha.c b/drivers/crypto/qce/sha.c
index fc72af8aa9a7..f850c6206a31 100644
--- a/drivers/crypto/qce/sha.c
+++ b/drivers/crypto/qce/sha.c
@@ -41,6 +41,7 @@ static void qce_ahash_done(void *data)
struct qce_sha_reqctx *rctx = ahash_request_ctx_dma(req);
struct qce_alg_template *tmpl = to_ahash_tmpl(async_req->tfm);
struct qce_device *qce = tmpl->qce;
+ struct qce_bam_transaction *qce_bam_txn = qce->dma.qce_bam_txn;
struct qce_result_dump *result = qce->dma.result_buf;
unsigned int digestsize = crypto_ahash_digestsize(ahash);
int error;
@@ -60,6 +61,17 @@ static void qce_ahash_done(void *data)
rctx->byte_count[0] = cpu_to_be32(result->auth_byte_count[0]);
rctx->byte_count[1] = cpu_to_be32(result->auth_byte_count[1]);
+ if (qce_bam_txn->qce_read_sgl_cnt)
+ dma_unmap_sg(qce->dev,
+ qce_bam_txn->qce_reg_read_sgl,
+ qce_bam_txn->qce_read_sgl_cnt,
+ DMA_DEV_TO_MEM);
+ if (qce_bam_txn->qce_write_sgl_cnt)
+ dma_unmap_sg(qce->dev,
+ qce_bam_txn->qce_reg_write_sgl,
+ qce_bam_txn->qce_write_sgl_cnt,
+ DMA_MEM_TO_DEV);
+
error = qce_check_status(qce, &status);
if (error < 0)
dev_dbg(qce->dev, "ahash operation error (%x)\n", status);
--
2.34.1
