On Thu, Dec 14, 2023 at 11:15:34AM +0100, Johan Hovold wrote:
> On Thu, Dec 14, 2023 at 02:40:45PM +0530, Manivannan Sadhasivam wrote:
>
> > This series fixes the clocks supplied to QMP PHY IPs in the Qcom SoCs. All
> > of the Qcom SoCs except MSM8996 require 3 clocks for QMP UFS:
> >
> > * ref - 19.2MHz reference clock from RPM/RPMh
> > * ref_aux - Auxiliary reference clock from GCC
> > * qref - QREF clock from GCC or TCSR (TCSR since SM8550)
> >
> > MSM8996 only requires 'ref' and 'qref' clocks.
> >
> > Hence, this series fixes the binding, DT and GCC driver to reflect the
> > actual clock topology.
>
> Is this based on documentation for all the SoCs or on inference from the
> current (upstream and downstream) devicetrees?
>
It is based on the internal documentation. Even downstream devicetrees are
wrong. I should've mentioned it in the cover letter.
> Are you sure that you should not just describe that some of these UFS
> reference clocks are sourced from CXO in the clock driver instead?
>
I don't get your comment fully. Could you please elaborate?
> Take a look at commits
>
> f446022b932a ("arm64: dts: qcom: sc8280xp: fix UFS reference clocks")
> f6abcc21d943 ("clk: qcom: gcc-sc8280xp: add cxo as parent for three ufs ref clks")
>
Btw, these commits are not accurate. In all the SoCs before SM8550, reference
clock for the UFS device comes from the UFS controller. There is a dedicated
register in UFSHC memory map that is being toggled by the driver to
enable/disable reference clock for the UFS device.
Since SM8550, reference clock is directly sourced from RPMh. I'm preparing a
series to fix it.
Unfortunately, this information is not depicted correctly in the downstream
devicetrees.
- Mani
> Johan
>
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