Re: [PATCH v2 1/2] drm/msm/dpu: Set input_sel bit for INTF

[Jessica Zhang <quic_jesszhan@xxxxxxxxxxx>]

On 12/13/2023 1:20 PM, Dmitry Baryshkov wrote:
> On Wed, 13 Dec 2023 at 22:51, Jessica Zhang <quic_jesszhan@xxxxxxxxxxx> wrote:
> > Set the input_sel bit for encoders as it was missed in the initial
> > implementation.
> >
> > Reported-by: Rob Clark <robdclark@xxxxxxxxx>
> > Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
> > Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
> > Signed-off-by: Jessica Zhang <quic_jesszhan@xxxxxxxxxxx>
> > ---
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c |  2 +-
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c   |  2 +-
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 10 ++++++++--
> >   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h |  3 ++-
> >   4 files changed, 12 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > index 0b6a0a7dcc39..226133af7840 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
> > @@ -322,7 +322,7 @@ static u32 dpu_hw_intf_get_line_count(struct dpu_hw_intf *intf)
> >
> >   static void dpu_hw_intf_setup_misr(struct dpu_hw_intf *intf, bool enable, u32 frame_count)
> >   {
> > -       dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count);
> > +       dpu_hw_setup_misr(&intf->hw, INTF_MISR_CTRL, enable, frame_count, 0x1);
> >   }
> >
> >   static int dpu_hw_intf_collect_misr(struct dpu_hw_intf *intf, u32 *misr_value)
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> > index 25af52ab602f..bbc9756ecde9 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> > @@ -85,7 +85,7 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_mixer *ctx,
> >
> >   static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx, bool enable, u32 frame_count)
> >   {
> > -       dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count);
> > +       dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, enable, frame_count, 0x0);
> >   }
> >
> >   static int dpu_hw_lm_collect_misr(struct dpu_hw_mixer *ctx, u32 *misr_value)
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> > index 0b05061e3e62..87716a60332e 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c
> > @@ -477,7 +477,8 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
> >
> >   void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
> >                  u32 misr_ctrl_offset,
> > -               bool enable, u32 frame_count)
> > +               bool enable, u32 frame_count,
> > +               u32 input_sel)
> >   {
> >          u32 config = 0;
> >
> > @@ -487,8 +488,13 @@ void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
> >          wmb();
> >
> >          if (enable) {
> > +               /*
> > +                * note: Aside from encoders, input_sel should be
> > +                * set to 0x0 by default
> > +                */
>
> Even if it is not a proper kernedoc, please move this comment before
> the function.

Acked.

> >                  config = (frame_count & MISR_FRAME_COUNT_MASK) |
> > -                       MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK;
> > +                       MISR_CTRL_ENABLE | MISR_CTRL_FREE_RUN_MASK |
> > +                       ((input_sel & 0xF) << 24);
> >
> >                  DPU_REG_WRITE(c, misr_ctrl_offset, config);
> >          } else {
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> > index fe083b2e5696..761056be272b 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h
> > @@ -357,7 +357,8 @@ void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset,
> >   void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c,
> >                  u32 misr_ctrl_offset,
> >                  bool enable,
> > -               u32 frame_count);
> > +               u32 frame_count,
> > +               u32 input_sel);
> >
> >   int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c,
> >                  u32 misr_ctrl_offset,
> >
> > --
> > 2.43.0
>
>
> --
> With best wishes
> Dmitry