For IPQ5332 platform, there are two MAC PCSs, and qca8084 is connected with one of them. 1. The Ethernet LDO needs to be enabled to make the PHY GPIO reset taking effect, which uses the MDIO bus level reset. 2. The SoC GCC uniphy AHB and SYS clocks need to be enabled to make the ethernet PHY device accessible. 3. To provide the clock to the ethernet, the CMN clock needs to be initialized for selecting reference clock and enabling the output clock. 4. Support optional MDIO clock frequency config. 5. Update dt-bindings doc for the new added properties. Changes in v2: * remove the PHY related features such as PHY address program and clock initialization. * leverage the MDIO level GPIO reset for qca8084 PHY. Luo Jie (5): net: mdio: ipq4019: move eth_ldo_rdy before MDIO bus register net: mdio: ipq4019: enable the SoC uniphy clocks for ipq5332 platform net: mdio: ipq4019: configure CMN PLL clock for ipq5332 net: mdio: ipq4019: support MDIO clock frequency divider dt-bindings: net: ipq4019-mdio: Document ipq5332 platform .../bindings/net/qcom,ipq4019-mdio.yaml | 157 +++++++++- drivers/net/mdio/mdio-ipq4019.c | 296 ++++++++++++++++-- 2 files changed, 424 insertions(+), 29 deletions(-) base-commit: abb240f7a2bd14567ab53e602db562bb683391e6 -- 2.42.0
