On Fri, Dec 08, 2023 at 11:55:02AM +0530, Sneh Shah wrote:
> SGMII 10MBPS mode needs RX clock divider to avoid drops in Rx.
> Update configure SGMII function with rx clk divider programming.
>
> Fixes: 463120c31c58 ("net: stmmac: dwmac-qcom-ethqos: add support for SGMII")
You didn't add my:
Tested-by: Andrew Halaney <ahalaney@xxxxxxxxxx>
from the last version. Typically that's fine to do even if you post a
new version as long as the changes are minor (in your case it's just the
comment that was added since I tested, so definitely fine to do).
> Signed-off-by: Sneh Shah <quic_snehshah@xxxxxxxxxxx>
> ---
> v3 changelog:
> - Added comment to explain why MAC needs to be reconfigured for SGMII
> v2 changelog:
> - Use FIELD_PREP to prepare bifield values in place of GENMASK
> - Add fixes tag
> ---
> drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> index d3bf42d0fceb..ab2245995bc6 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
> @@ -34,6 +34,7 @@
> #define RGMII_CONFIG_LOOPBACK_EN BIT(2)
> #define RGMII_CONFIG_PROG_SWAP BIT(1)
> #define RGMII_CONFIG_DDR_MODE BIT(0)
> +#define RGMII_CONFIG_SGMII_CLK_DVDR GENMASK(18, 10)
>
> /* SDCC_HC_REG_DLL_CONFIG fields */
> #define SDCC_DLL_CONFIG_DLL_RST BIT(30)
> @@ -598,6 +599,9 @@ static int ethqos_configure_rgmii(struct qcom_ethqos *ethqos)
> return 0;
> }
>
> +/* On interface toggle MAC registetrs gets reset.
> + * Configure MAC block for SGMII on ethernet phy link up
> + */
s/registetrs/registers/
> static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
> {
> int val;
> @@ -617,6 +621,9 @@ static int ethqos_configure_sgmii(struct qcom_ethqos *ethqos)
> case SPEED_10:
> val |= ETHQOS_MAC_CTRL_PORT_SEL;
> val &= ~ETHQOS_MAC_CTRL_SPEED_MODE;
> + rgmii_updatel(ethqos, RGMII_CONFIG_SGMII_CLK_DVDR,
> + FIELD_PREP(RGMII_CONFIG_SGMII_CLK_DVDR, 0x31),
> + RGMII_IO_MACRO_CONFIG);
> break;
> }
>
> --
> 2.17.1
>
