On Thu, Dec 07, 2023 at 05:37:19PM +0100, Neil Armstrong wrote:
> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
[..]
> +
> + mdss_dp0: displayport-controller@af54000 {
> + compatible = "qcom,sm8650-dp";
> + reg = <0 0xaf54000 0 0x200>,
> + <0 0xaf54200 0 0x200>,
> + <0 0xaf55000 0 0xc00>,
> + <0 0xaf56000 0 0x400>,
> + <0 0xaf57000 0 0x400>;
> +
> + interrupts-extended = <&mdss 12>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + operating-points-v2 = <&dp_opp_table>;
> +
> + power-domains = <&rpmhpd RPMHPD_MX>;
Are you sure the DP TX block sits in MX? I'd expect this to be
RPMHPD_MMCX, and then the PHY partially in MX...
> +
> + phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + mdss_dp0_in: endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mdss_dp0_out: endpoint {
> + };
> + };
> + };
> +
> + dp_opp_table: opp-table {
Is there any reason why we keep sorting 'o' after 'p' in these nodes?
Regards,
Bjorn
