On Wed, 6 Dec 2023 at 00:06, Rob Clark <robdclark@xxxxxxxxx> wrote:
>
> From: Rob Clark <robdclark@xxxxxxxxxxxx>
>
> Introduce a6xx_info where we can stash gen specific stuff without
> polluting the toplevel adreno_info struct.
>
> Signed-off-by: Rob Clark <robdclark@xxxxxxxxxxxx>
> ---
> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 55 +++++++++++++++++------
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 4 +-
> drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 9 ++++
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++-
> 4 files changed, 58 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index a35d4c112a61..3fb9e249567a 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -7,6 +7,7 @@
> */
>
> #include "adreno_gpu.h"
> +#include "a6xx_gpu.h"
> #include "a6xx.xml.h"
> #include "a6xx_gmu.xml.h"
>
> @@ -465,7 +466,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a610_zap.mdt",
> - .hwcg = a612_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a612_hwcg,
> + },
> /*
> * There are (at least) three SoCs implementing A610: SM6125
> * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does
> @@ -492,6 +495,8 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> + .a6xx = &(struct a6xx_info) {
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 169, 1 },
> @@ -510,7 +515,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> - .hwcg = a615_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a615_hwcg,
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 138, 1 },
> @@ -529,7 +536,9 @@ const struct adreno_info a6xx_gpus[] = {
> .inactive_period = DRM_MSM_INACTIVE_PERIOD,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> - .hwcg = a615_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a615_hwcg,
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 190, 1 },
> @@ -548,7 +557,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a615_zap.mdt",
> - .hwcg = a615_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a615_hwcg,
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 120, 4 },
> @@ -572,7 +583,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a630_zap.mdt",
> - .hwcg = a630_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a630_hwcg,
> + },
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06040001),
> .family = ADRENO_6XX_GEN2,
> @@ -586,7 +599,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> - .hwcg = a640_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a640_hwcg,
> + },
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> { 1, 1 },
> @@ -605,7 +620,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a650_zap.mdt",
> - .hwcg = a650_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a650_hwcg,
> + },
> .address_space_size = SZ_16G,
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> @@ -627,7 +644,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a660_zap.mdt",
> - .hwcg = a660_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a660_hwcg,
> + },
> .address_space_size = SZ_16G,
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06030500),
> @@ -642,7 +661,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a660_zap.mbn",
> - .hwcg = a660_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a660_hwcg,
> + },
> .address_space_size = SZ_16G,
> .speedbins = ADRENO_SPEEDBINS(
> { 0, 0 },
> @@ -663,7 +684,9 @@ const struct adreno_info a6xx_gpus[] = {
> .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT,
> .init = a6xx_gpu_init,
> .zapfw = "a640_zap.mdt",
> - .hwcg = a640_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a640_hwcg,
> + },
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x06090000),
> .family = ADRENO_6XX_GEN4,
> @@ -677,7 +700,9 @@ const struct adreno_info a6xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a690_zap.mdt",
> - .hwcg = a690_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a690_hwcg,
> + },
> .address_space_size = SZ_16G,
> }, {
> /* sentinal */
> @@ -822,7 +847,9 @@ const struct adreno_info a7xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a730_zap.mdt",
> - .hwcg = a730_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a730_hwcg,
> + },
> .address_space_size = SZ_16G,
> }, {
> .chip_ids = ADRENO_CHIP_IDS(0x43050a01), /* "C510v2" */
> @@ -837,7 +864,9 @@ const struct adreno_info a7xx_gpus[] = {
> ADRENO_QUIRK_HAS_HW_APRIV,
> .init = a6xx_gpu_init,
> .zapfw = "a740_zap.mdt",
> - .hwcg = a740_hwcg,
> + .a6xx = &(struct a6xx_info) {
> + .hwcg = a740_hwcg,
> + },
> .address_space_size = SZ_16G,
> }, {
> /* sentinal */
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index e0414d0753ad..a064eb42eedd 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -403,7 +403,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> unsigned int i;
> u32 val, clock_cntl_on, cgc_mode;
>
> - if (!adreno_gpu->info->hwcg)
> + if (!adreno_gpu->info->a6xx->hwcg)
> return;
>
> if (adreno_is_a630(adreno_gpu))
> @@ -434,7 +434,7 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
> if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu))
> gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
>
> - for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
> + for (i = 0; (reg = &adreno_gpu->info->a6xx->hwcg[i], reg->offset); i++)
> gpu_write(gpu, reg->offset, state ? reg->value : 0);
>
> /* Enable SP clock */
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> index 34822b080759..1840c1f3308e 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
> @@ -12,6 +12,15 @@
>
> extern bool hang_debug;
>
> +/**
> + * struct a6xx_info - a6xx specific information from device table
> + *
> + * @hwcg: hw clock gating register sequence
> + */
> +struct a6xx_info {
> + const struct adreno_reglist *hwcg;
> +};
> +
> struct a6xx_gpu {
> struct adreno_gpu base;
>
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index 5d094c5ec363..cba53203de98 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -81,6 +81,8 @@ struct adreno_speedbin {
> uint16_t speedbin;
> };
>
> +struct a6xx_info;
> +
> struct adreno_info {
> const char *machine;
> /**
> @@ -97,7 +99,9 @@ struct adreno_info {
> struct msm_gpu *(*init)(struct drm_device *dev);
> const char *zapfw;
> u32 inactive_period;
> - const struct adreno_reglist *hwcg;
> + union {
> + const struct a6xx_info *a6xx;
> + };
I think the usual pattern is to subclass the common structure rather
than adding a polymorphic field.
So, from my point of view, it should be:
struct a6xx_info {
struct adreno_info base;
struct areno_reglist *hwcg;
};
> u64 address_space_size;
> /**
> * @speedbins: Optional table of fuse to speedbin mappings
> --
> 2.42.0
>
--
With best wishes
Dmitry
