On 11/14/23 14:56, Bibek Kumar Patro wrote:
Context caching is re-enabled in the prefetch buffer for Qualcomm SoCs through SoC specific reset ops, which is disabled in the default MMU-500 reset ops, but is expected for context banks using ACTLR register to retain the prefetch value during reset and runtime suspend. Signed-off-by: Bibek Kumar Patro <quic_bibekkum@xxxxxxxxxxx> ---
And I assume that goes for all SMMU500 implementations? Looking at the 8550 ACTRL array from patch 2, CPRE is not enabled at all times.. Is that because of performance, or some other technical reason? Will this regress platforms without ACTRL tables? Konrad
