On Tue, Nov 07, 2023 at 06:34:53PM +0530, Mrinmay Sarkar wrote:
> Add ep pcie dtsi node for pcie1 controller found on sa8775p platform.
> It supports gen4 and x4 link width. Limiting the speed to Gen3 due to
> stability issues.
I wouldn't mind a bit more information on what "stability" issues
entails! I'm a sucker for details in a commit message.
>
> Signed-off-by: Mrinmay Sarkar <quic_msarkar@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 48 +++++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> index 7eab458..acd7bd8 100644
> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
> @@ -3732,6 +3732,54 @@
> status = "disabled";
> };
>
> + pcie1_ep: pcie-ep@1c10000 {
> + compatible = "qcom,sa8775p-pcie-ep";
> + reg = <0x0 0x01c10000 0x0 0x3000>,
> + <0x0 0x60000000 0x0 0xf20>,
> + <0x0 0x60000f20 0x0 0xa8>,
> + <0x0 0x60001000 0x0 0x4000>,
> + <0x0 0x60200000 0x0 0x100000>,
> + <0x0 0x01c13000 0x0 0x1000>,
> + <0x0 0x60005000 0x0 0x2000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
> + "mmio", "dma";
> +
> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
> +
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a";
> +
> + interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
> +
> + interrupt-names = "global", "doorbell", "dma";
> +
> + interconnects = <&pcie_anoc MASTER_PCIE_1 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_1 0>;
I keep seeing Konrad requesting that we use the #define instead of a raw
number 0, i.e. something like QCOM_ICC_TAG_ALWAYS (although if I'm
reading that correctly QCOM_ICC_TAG_ALWAYS doesn't evaluate to 0, so
make sure you pick the appropriate one).
> + interconnect-names = "pcie-mem", "cpu-pcie";
This is nitpicky, but unless someone told you to do the whitespace
between some of these properties I'd get more consistent. i.e. reg and
reg-names has no newline between them, but clocks and clock-names does,
and then interconnects/interconnect-names does not.
> +
> + dma-coherent;
> +
> + iommus = <&pcie_smmu 0x80 0x7f>;
> + resets = <&gcc GCC_PCIE_1_BCR>;
> + reset-names = "core";
> + power-domains = <&gcc PCIE_1_GDSC>;
> + phys = <&pcie1_phy>;
> + phy-names = "pciephy";
> + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */
> + num-lanes = <4>;
> +
> + status = "disabled";
> + };
> +
> pcie1_phy: phy@1c14000 {
> compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy";
> reg = <0x0 0x1c14000 0x0 0x4000>;
> --
> 2.7.4
>
>
