On Mon, 30 Oct 2023 at 22:12, Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> wrote: > > On 30.10.2023 21:37, Robert Marko wrote: > > On Mon, 30 Oct 2023 at 20:37, Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> wrote: > >> > >> On 29.10.2023 12:04, Robert Marko wrote: > >>> On Wed, 25 Oct 2023 at 12:45, Robert Marko <robimarko@xxxxxxxxx> wrote: > >>>> > >>>> IPQ6018 has GDSC-s for each of the USB ports, so lets define them as such > >>>> and drop the curent code that is de-asserting the USB GDSC-s as part of > >>>> the GCC probe. > >>>> > >>>> Signed-off-by: Robert Marko <robimarko@xxxxxxxxx> > >>> > >>> Unfortunately, after testing on multiple devices I hit the same GDSC > >>> issue I had a long time ago > >>> that was the reason I did not send this upstream. > >>> It seems that USB3 port GDSC (USB0 GDSC in code) works just fine, > >>> however the USB2 one > >>> (USB1 GDSC in code) it is stuck off and USB2 port will fail due to this: > >>> 1.607531] ------------[ cut here ]------------ > >>> [ 1.607559] usb1_gdsc status stuck at 'off' > >>> [ 1.607592] WARNING: CPU: 0 PID: 35 at gdsc_toggle_logic+0x16c/0x174 > >>> [ 1.615120] Modules linked in: > >> Can you dump GDSCR (the entire 32-bit register) at boot and when toggling? > > > > Sure, here it is: > > [ 0.023760] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: 0x8222004 init > > [ 0.023782] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: 0x8222004 init > > [ 0.988626] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: > > 0x8282000 before toggle > > [ 1.202506] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3f078 val: > > 0x8282000 after toggle > > [ 1.207208] qcom,gcc-ipq6018 1800000.gcc: reg: 0x3e078 val: > > 0xa0282000 before toggle > Any chance > > .en_few_wait_val = 0x2 > > (turning BIT(19) into BIT(17)) > > will make a difference? Sadly, it makes no difference and GDSC status bit newer comes up which is rather weird as USB0 one seems to work just fine. Regards, Robert > > Konrad
